View W25Q32JVTCIQ_8932085.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w25q32jv publication release date: november 18, 2014 preliminary-revision a1 3v 32m-bit serial flash memory with dual, quad spi
w25q32jv - 1 - table of contents 1. general descriptions .............................. ................................................... ....................... 4 2. features .......................................... ................................................... .................................... 4 3. package types and pin configurations .............. ................................................... ...... 5 3.1 pin configuration soic 208-mil / vsop 208-mil ..... ................................................... ....... 5 3.2 pad configuration wson 6x5-mm ..................... ................................................... ........... 5 3.3 pin description soic / vsop 208-mil, wson 6x5-mm .. .................................................. 5 3.4 pin configuration soic 300-mil .................... ................................................... ................ 6 3.5 pin description soic 300-mil ...................... ................................................... .................. 6 3.6 ball configuration tfbga 8x6-mm (6x4 ball array) .. ................................................... ..... 7 3.7 ball description tfbga 8x6-mm ..................... ................................................... .............. 7 3.8 pin configuration pdip 300-mil .................... ................................................... ................. 8 3.9 pin description pdip 300-mil ...................... ................................................... .................. 8 4. pin descriptions .................................. ................................................... .............................. 9 4.1 chip select (/cs) ................................. ................................................... ......................... 9 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) ................................... 9 4.3 write protect (/wp) ............................... ................................................... ........................ 9 4.4 hold (/hold) ...................................... ................................................... ....................... 9 4.5 serial clock (clk) ................................ ................................................... ........................ 9 4.6 reset (/reset) .................................... ................................................... ........................ 9 5. block diagram ..................................... ................................................... ............................. 10 6. functional descriptions............................ ................................................... .................. 11 6.1 standard spi instructions.......................... ................................................... .................. 11 6.2 dual spi instructions ............................. ................................................... ..................... 11 6.3 quad spi instructions ............................. ................................................... .................... 11 6.4 hold function ..................................... ................................................... ........................ 11 6.5 software reset & hardware /reset pin .............. ................................................... ....... 12 6.6 write protection .................................. ................................................... ........................ 13 write protect features ............................ ................................................... ........................... 13 7. status and configuration registers ................ ................................................... ...... 14 7.1 status registers .................................. ................................................... ....................... 14 erase/write in progress (busy) C status only .................................................. .................. 14 write enable latch (wel) C status only .................................................. ............................ 14 block protect bits (bp2, bp1, bp0) C volatile/non-volatile writable .................................... 14 top/bottom block protect (tb) C volatile/non-volatile writable ........................................... 15 sector/block protect bit (sec) C volatile/non-volatile writable ........................................... 15 complement protect (cmp) C volatile/non-volatile writable ................................................ 1 5 status register protect (srp, srl) ................ ................................................... .................. 16 erase/program suspend status (sus) C status only .................................................. ........ 17 security register lock bits (lb3, lb2, lb1) C volatile/non-volatile otp writable ............ 17 quad enable (qe) C volatile/non-volatile writable .................................................. .......... 17 write protect selection (wps) C volatile/non-volatile writable .......................................... 18 output driver strength (drv1, drv0) C volatile/non-volatile writable ............................. 18
w25q32jv publication release date: november 18, 2014 - 2 - preliminary-revision a1 /hold or /reset pin function (hold/rst) C volatile/non-volatile writable .................. 18 reserved bits C non functional .................................................. ....................................... 18 status register memory protection (wps = 0, cmp = 0 ) ................................................. .. 19 status register memory protection (wps = 0, cmp = 1 ) ................................................. .. 20 individual block memory protection (wps=1) ........ ................................................... ......... 21 8. instructions ...................................... ................................................... ............................... 22 8.1 device id and instruction set tables............... ................................................... ............ 22 manufacturer and device identification ............ ................................................... .................. 22 instruction set table 1 (standard spi instructions) (1) .................................................. ......... 23 instruction set table 2 (dual/quad spi instructions ) (1) .................................................. ....... 24 8.2 instruction descriptions .......................... ................................................... ..................... 25 write enable (06h) ................................ ................................................... ............................. 25 write enable for volatile status register (50h) ... ................................................... ............... 25 write disable (04h) ............................... ................................................... ............................. 26 read status register-1 (05h), status register-2 (35 h) & status register-3 (15h) ............... 27 write status register-1 (01h), status register-2 (3 1h) & status register-3 (11h) ............... 27 read data (03h) ................................... ................................................... ............................. 29 fast read (0bh) ................................... ................................................... ............................. 30 fast read dual output (3bh) ....................... ................................................... ..................... 31 fast read quad output (6bh) ....................... ................................................... .................... 32 fast read dual i/o (bbh) .......................... ................................................... ...................... 33 fast read quad i/o (ebh) .......................... ................................................... ..................... 35 set burst with wrap (77h) ......................... ................................................... ....................... 37 page program (02h) ................................ ................................................... ........................ 38 quad input page program (32h) ..................... ................................................... ................. 39 sector erase (20h) ................................ ................................................... ........................... 40 32kb block erase (52h) ............................ ................................................... ....................... 41 64kb block erase (d8h) ............................ ................................................... ...................... 42 chip erase (c7h / 60h) ............................ ................................................... ........................ 43 erase / program suspend (75h) ..................... ................................................... ................. 44 erase / program resume (7ah) ...................... ................................................... ................. 45 power-down (b9h) .................................. ................................................... ......................... 46 release power-down / device id (abh) .............. ................................................... ............ 47 read manufacturer / device id (90h) ............... ................................................... ............... 48 read manufacturer / device id dual i/o (92h) ...... ................................................... .......... 49 read manufacturer / device id quad i/o (94h) ...... ................................................... ......... 50 read unique id number (4bh) ....................... ................................................... ................. 51 read jedec id (9fh) ............................... ................................................... ...................... 52 read sfdp register (5ah) .......................... ................................................... .................... 53 erase security registers (44h) .................... ................................................... .................... 54 program security registers (42h) .................. ................................................... .................. 55 read security registers (48h) ..................... ................................................... .................... 56 individual block/sector lock (36h) ................ ................................................... ................... 57 individual block/sector unlock (39h) .............. ................................................... ................. 58 read block/sector lock (3dh) ...................... ................................................... ................... 59
w25q32jv - 3 - global block/sector lock (7eh) .................... ................................................... ................... 60 global block/sector unlock (98h) .................. ................................................... .................. 60 enable reset (66h) and reset device (99h) ......... ................................................... .......... 61 9. electrical characteristics......................... ................................................... ............... 62 9.1 absolute maximum ratings (1) .................................................. .................................... 62 9.2 operating ranges .................................. ................................................... ..................... 62 9.3 power-up power-down timing and requirements ....... .................................................. 63 9.4 dc electrical characteristics- .................... ................................................... .................. 64 9.5 ac measurement conditions.......................... ................................................... ............. 65 9.6 ac electrical characteristics (6) .................................................. ..................................... 66 9.7 serial output timing .............................. ................................................... ..................... 68 9.8 serial input timing ............................... ................................................... ....................... 68 9.9 /hold timing ...................................... ................................................... ....................... 68 9.10 wp timing ......................................... ................................................... ......................... 68 10. package specifications ............................ ................................................... .................... 69 10.1 8-pin soic 208-mil (package code ss) .............. ................................................... ....... 69 10.2 8-pin vsop 208-mil (package code st) .............. ................................................... ...... 70 10.3 8-pad wson 6x5-mm (package code zp) ............... ................................................... .. 71 10.5 16-pin soic 300-mil (package code sf) ............. ................................................... ....... 72 10.6 8-pin pdip 300-mil (package code da)............... ................................................... ....... 73 10.8 24-ball tfbga 8x6-mm (package code tc, 6x4 ball arr ay) ........................................... 74 11. ordering information .............................. ................................................... ..................... 75 11.1 valid part numbers and top side marking ........... ................................................... ....... 76 12. revision history .................................. ................................................... ............................ 77
w25q32jv publication release date: november 18, 2014 - 4 - preliminary-revision a1 1. general descriptions the w25q32jv (32m-bit) serial flash memory provides a storage solution for systems with limited space, pins and power. the 25q series offers flexibility a nd performance well beyond ordinary serial flash de vices. they are ideal for code shadowing to ram, executing code directly from dual/quad spi (xip) and storing voice, text and data. the device operates on 2.7v t o 3.6v power supply with current consumption as low as 1a for power-down. all devices are offered in s pace-saving packages. the w25q32jv array is organized into 16,384 program mable pages of 256-bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4kb sector erase), groups of 128 (32kb block erase), groups of 256 (64kb block erase ) or the entire chip (chip erase). the w25q32jv has 1,024 erasable sectors and 64 erasable blocks respe ctively. the small 4kb sectors allow for greater flexibility in applications that require data and p arameter storage. (see figure 2.) the w25q32jv supports the standard serial periphera l interface (spi), dual/quad i/o spi: serial clock, chip select, serial data i/o0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold). spi clock frequencies of w25q32jv of up to 133mhz are supported allowing equ ivalent clock rates of 266mhz (133mhz x 2) for dual i/o and 532mhz (133mhz x 4) for quad i/o when using the fast read dual/quad i/o. these transfer rates can outperform standard asynchronous 8 and 16 -bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-b it address, allowing true xip (execute in place) opera tion. a hold pin, write protect pin and programmable writ e protection, with top or bottom array control, pro vide further control flexibility. additionally, the devi ce supports jedec standard manufacturer and device id, and a 64-bit unique serial number and three 256-byt es security registers. 2. features new family of spiflash memories C w25q32jv: 32m-bit / 4m-byte C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 C software & hardware reset highest performance serial flash C more than 100,000 erase/program cycles C min. 100k program-erase cycles per sector C 133mhz single, dual/quad spi clocks 266/532mhz equivalent dual/quad spi efficient continuous read C continuous read with 8/16/32/64-byte wrap C as few as 8 clocks to address memory C allows true xip (execute in place) operation C outperforms x16 parallel flash low power, wide temperature range C single 2.7 to 3.6v supply C <1a power-down (typ.) C -40c to +85c operating range flexible architecture with 4kb sectors C uniform sector/block erase (4k/32k/64k-byte) C program 1 to 256 byte per programmable page C erase/program suspend & resume advanced security features C software and hardware write-protect C special otp protection (1) C top/bottom, complement array protection C individual block/sector array protection C 64-bit unique id for each device C discoverable parameters (sfdp) register C 3x256-bytes security registers C volatile & non-volatile status register bits space efficient packaging C 8-pin soic 208-mil / vsop 208-mil C 8-pad wson 6x5-mm C 16-pin soic 300-mil C 8-pin pdip 300-mil C 24-ball tfbga 8x6-mm (6x4 ball array) C contact winbond for kgd and other options
w25q32jv - 5 - 3. package types and pin configurations 3.1 pin configuration soic 208-mil / vsop 208-mil figure 1a. w25q32jv pin assignments, 8-pin soic / v sop 208-mil (package code ss / st) 3.2 pad configuration wson 6x5-mm figure 1b. w25q32jv pad assignments, 8-pad wson 6x5 -mm (package code zp) 3.3 pin description soic / vsop 208-mil, wson 6x5-m m pin no. pin name i/o function 1 /cs i chip select input 2 do (io1) i/o data output (data input output 1) (1) 3 /wp (io2) i/o write protect input ( data input output 2) (2) 4 gnd ground 5 di (io0) i/o data input (data input output 0) (1) 6 clk i serial clock input 7 /hold or /reset (io3) i/o hold or reset input (data input output 3) (2) 8 vcc power supply notes: 1. io0 and io1 are used for standard and dual spi i nstructions 2. io0 C io3 are used for quad spi instructions, /w p & /hold (or /reset) functions are only available for standard/dual spi.
w25q32jv publication release date: november 18, 2014 - 6 - preliminary-revision a1 3.4 pin configuration soic 300-mil figure 1c. w25q32jv pin assignments, 16-pin soic 30 0-mil (package code sf) 3.5 pin description soic 300-mil pin no. pin name i/o function 1 /hold (io3) i/o hold input (data input output 3) (2) 2 vcc power supply 3 /reset i reset input (3) 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/o data output (data input output 1) (1) 9 /wp (io2) i/o write protect input (data input output 2) (2) 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di (io0) i/o data input (data input output 0) (1) 16 clk i serial clock input notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, / wp & /hold (or /reset) functions are only available for standard/dual spi. 3. the /reset pin on soic-16 package is independen t of the hold/rst bit and qe bit settings in the st atus register. this pin can be left floating, if rest function is not neede d.
w25q32jv - 7 - 3.6 ball configuration tfbga 8x6-mm (6x4 ball array ) figure 1d. w25q32jv ball assignments, 24-ball tfbga 8x6-mm (package code tc) 3.7 ball description tfbga 8x6-mm ball no. pin name i/o function a4 /reset i reset input (3) b2 clk i serial clock input b3 gnd ground b4 vcc power supply c2 /cs i chip select input c4 /wp (io2) i/o write protect input (data input output 2) (2) d2 do (io1) i/o data output (data input output 1) (1) d3 di (io0) i/o data input (data input output 0) (1) d4 /hold (io3) i/o hold input (data input output 3) (2) multiple nc no connect notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, / wp & /hold functions are only available for standar d/dual spi. 3. the /reset pin on soic-16 package is independen t of the hold/rst bit and qe bit settings in the st atus register. this pin can be left floating, if rest function is not neede d.
w25q32jv publication release date: november 18, 2014 - 8 - preliminary-revision a1 3.8 pin configuration pdip 300-mil figure 1e. w25q32jv pin assignments, 8-pin pdip (pa ckage code da) 3.9 pin description pdip 300-mil pin no. pin name i/o function 1 /cs i chip select input 2 do (io1) i/o data output (data input output 1) (1) 3 /wp (io2) i/o write protect input ( data input output 2) (2) 4 gnd ground 5 di (io0) i/o data input (data input output 0) (1) 6 clk i serial clock input 7 /hold or /reset (io3) i/o hold or reset input (data input output 3) (2) 8 vcc power supply notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions, / wp & /hold (or /reset) functions are only available for standard/dual spi.
w25q32jv - 9 - 4. pin descriptions 4.1 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do, or io0, io1, io2, io3) pins are at high impedance. when deselected, the devices power consumption will be a t standby levels unless an internal erase, program or write status register cycle is in progress. when /c s is brought low the device will be selected, power consumption will increase to active levels and inst ructions can be written to and data read from the d evice. after power-up, /cs must transition from high to low before a new instr uction will be accepted. the /cs input must track the vcc supply level at power-up a nd power-down (see write protection and figure 58 ). if needed a pull-up resister on the /cs pin can be used to accomplish this. 4.2 serial data input, output and ios (di, do and i o0, io1, io2, io3) the w25q32jv supports standard spi, dual spi and qu ad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write instructions, addresses or data to the device on t he rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to rea d data or status from the device on the falling edge of cl k. dual and quad spi instructions use the bidirectiona l io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read da ta or status from the device on the falling edge of clk. quad spi instructions require the non-volatile quad enable bit (qe) in status register-2 to be set. w hen qe=1, the /wp pin becomes io2 and /hold pin becomes io3. 4.3 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protec t (cmp, sec, tb, bp2, bp1 and bp0) bits and status register protect (srp) bits, a portion as small as a 4kb sector or the entire memory array can be hard ware protected. the /wp pin is active low. when the qe b it of status register-2 is set for quad i/o, the /w p pin function is not available since this pin is used fo r io2. see figure 1a-c for the pin configuration of quad i/o operation. 4.4 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and si gnals on the di and clk pins will be ignored (dont care). when /hold is brought high, device op eration can resume. the /hold function can be useful when multiple devices are sharing the same spi sign als. the /hold pin is active low. when the qe bit o f status register-2 is set for quad i/o, the /hold pi n function is not available since this pin is used for io3. see figure 1a-e for the pin configuration of quad i /o operation. 4.5 serial clock (clk) the spi serial clock input (clk) pin provides the t iming for serial input and output operations. ("see spi operations") 4.6 reset (/reset) the /reset pin allows the device to be reset by the controller. for 8-pin packages, when qe=0, the io3 pin can be configured either as a /hold pin or as a /reset pin depending on status register setting. when qe=1, the /hold or /reset function is not avai lable for 8-pin configuration. on the 16-pin soic package, a dedicated /reset pin is provided and it is independent of qe bit setting.
w25q32jv publication release date: november 18, 2014 - 10 - preliminary-revision a1 5. block diagram figure 2. w25q32jv serial flash memory block diagra m 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256-byte page buffer beginning page address ending page address w25q32fv spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ?? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ?? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ?? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 20ff00h 20ffffh ? block 32 (64kb) ? 200000h 2000ffh ?? ? 3fff00h 3fffffh ? block 63 (64kb) ? 3f0000h 3f00ffh /hold (io 3 ) or /reset (io 3 ) w25q32jv
w25q32jv - 11 - 6. functional descriptions 6.1 standard spi instructions the w25q32jv is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) and seria l data output (do). standard spi instructions use t he di input pin to serially write instructions, addresses or data to the device on the rising edge of clk. t he do output pin is used to read data or status from the device on the falling edge of clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supp orted. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is n ot being transferred to the serial flash. for mode 0, the clk signal is normally low on the falling and r ising edges of /cs. for mode 3, the clk signal is normall y high on the falling and rising edges of /cs. 6.2 dual spi instructions the w25q32jv supports dual spi operation when using instructions such as fast read dual output (3bh) and fast read dual i/o (bbh). these instru ctions allow data to be transferred to or from the device at two to three times the rate of ordinary serial f lash devices. the dual spi read instructions are id eal for quickly downloading code to ram upon power-up (code -shadowing) or for executing non-speed-critical code directly from the spi bus (xip). when using du al spi instructions, the di and do pins become bidirectional i/o pins: io0 and io1. 6.3 quad spi instructions the w25q32jv supports quad spi operation when using instructions such as fast read quad output (6bh), and fast read quad i/o (ebh). these instru ctions allow data to be transferred to or from the device four to six times the rate of ordinary serial flash . the quad read instructions offer a significant improvement in continuous and random access transfe r rates allowing fast code-shadowing to ram or execution directly from the spi bus (xip). when usi ng quad spi instructions the di and do pins become bidirectional io0 and io1, and the /wp and /hold pi ns become io2 and io3 respectively. quad spi instructions require the non-volatile quad enable b it (qe) in status register-2 to be set. 6.4 hold function for standard spi and dual spi operations, the /hold signal allows the w25q32jv operation to be paused while it is actively selected (when /cs is low). th e /hold function may be useful in cases where the spi data and clock signals are shared with other device s. for example, consider if the page buffer was onl y partially written when a priority interrupt require s use of the spi bus. in this case the /hold function can save the state of the instruction and the data in t he buffer so programming can resume where it left o ff once the bus is available again. the /hold function is o nly available for standard spi and dual spi operati on, not during quad spi. the quad enable bit qe in stat us register-2 is used to determine if the pin is us ed as /hold pin or data i/o pin. when qe=0 (factory de fault), the pin is /hold, when qe=1, the pin will become an i/o pin, /hold function is no longer avai lable. to initiate a /hold condition, the device must be selected with /cs low . a /hold condition will activate on the falling edge of the /hold signal if the clk sig nal is already low. if the clk is not already low t he /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data input (di) and seri al clock (clk) are ignored. the chip select (/cs) signal should be kept active (low) for the full dur ation of the /hold operation to avoid resetting the internal logic state of the device.
w25q32jv publication release date: november 18, 2014 - 12 - preliminary-revision a1 6.5 software reset & hardware /reset pin the w25q32jv can be reset to the initial power-on s tate by a software reset sequence in spi mode. this sequence must include two consecutive commands: ena ble reset (66h) & reset (99h). if the command sequence is successfully accepted, the device will take approximately 30us ( t rst ) to reset. no command will be accepted during the reset period. for the wson-8 and tfbga package types, w25q32jv ca n also be configured to utilize a hardware /reset pin. the hold/rst bit in the status register -3 is the configuration bit for /hold pin function or reset pin function. when hold/rst=0 (factory defaul t), the pin acts as a /hold pin as described above; when hold/rst=1, the pin acts as a /reset pin. driv e the /reset pin low for a minimum period of ~1us (treset*) will reset the device to its initial powe r-on state. any on-going program/erase operation wi ll be interrupted and data corruption may happen. while / reset is low, the device will not accept any comman d input. if qe bit is set to 1, the /hold or /reset function will be disabled, the pin will become one of the f our data i/o pins. for the soic-16 and tfbga-24 packages, w25q32jv pro vides a dedicated /reset pin in addition to the /hold (io 3 ) pin as illustrated in figure 1c/1d. drive the /re set pin low for a minimum period of ~1us (treset*) will reset the device to its initial powe r-on state. the hold/rst bit or qe bit in the statu s register will not affect the function of this dedic ated /reset pin. hardware /reset pin has the highest priority among all the input signals. drive /reset low for a minim um period of ~1us (treset*) will interrupt any on-goin g external/internal operations, regardless the stat us of other spi signals (/cs, clk, ios, /wp and/or /hold) . note: 1. while a faster /reset pulse (as short as a few h undred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation. 2. there is an internal pull-up resistor for the de dicated /reset pin on the soic-16 and tfbga-24 pack age. if the reset function is not needed, this pin can be left floating in the sy stem.
w25q32jv - 13 - 6.6 write protection applications that use non-volatile memory must take into consideration the possibility of noise and ot her adverse system conditions that may compromise data integrity. to address this concern, the w25q32jv provides several means to protect the data from ina dvertent writes. write protect features device resets when vcc is below threshold time delay write disable after power-up write enable/disable instructions and automatic wr ite disable after erase or program software and hardware (/wp pin) write protection u sing status registers additional individual block/sector locks for array protection write protection using power-down instruction lock down write protection for status register unt il the next power-up one time program (otp) write protection for array and security registers using status register * * note: this feature is available upon special order. pleas e contact winbond for details. upon power-up or at power-down, the w25q32jv will m aintain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figur e 43). while reset, all operations are disabled and no instructions are rec ognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are fu rther disabled for a time delay of t puw . this includes the write enable, page program, sector era se, block erase, chip erase and the write status register instructions. note that the chip select pi n (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached, and it must also track the vcc supply level at power- down to prevent adverse command sequence. if needed a pull-up resister on /cs can be used to accomplish this. after power-up the device is automatically placed i n a write-disabled state with the status register w rite enable latch (wel) set to a 0. a write enable instr uction must be issued before a page program, sector erase, block erase, chip erase or write status regi ster instruction will be accepted. after completing a program, erase or write instruction the write enabl e latch (wel) is automatically cleared to a write-d isabled state of 0. software controlled write protection is facilitated using the write status register instruction and se tting the status register protect (srp, srl) and block protec t (cmp, sec, tb, bp[2:0]) bits. these settings allo w a portion or the entire memory array to be configur ed as read only. used in conjunction with the write protect (/wp) pin, changes to the status register c an be enabled or disabled under hardware control. s ee status register section for further information. ad ditionally, the power-down instruction offers an ex tra level of write protection as all instructions are ignored except for the release power-down instruction. the w25q32jv also provides another write protect me thod using the individual block locks. each 64kb block (except the top and bottom blocks, total of 5 10 blocks) and each 4kb sector within the top/botto m blocks (total of 32 sectors) are equipped with an i ndividual block lock bit. when the lock bit is 0, t he corresponding sector or block can be erased or prog rammed; when the lock bit is set to 1, erase or pro gram commands issued to the corresponding sector or bloc k will be ignored. when the device is powered on, a ll individual block lock bits will be 1, so the entire memory array is protected from erase/program. an individual block unlock (39h) instruction must be issued to unlock any specific sector or block. the wps bit in status register-3 is used to decide which write protect scheme should be used. when wps=0 (factory default), the device will only utili ze cmp, sec, tb, bp[2:0] bits to protect specific a reas of the array; when wps=1, the device will utilize the individual block locks for write protection.
w25q32jv publication release date: november 18, 2014 - 14 - preliminary-revision a1 7. status and configuration registers three status and configuration registers are provid ed for w25q32jv. the read status register-1/2/3 instructions can be used to provide status on the a vailability of the flash memory array, whether the device is write enabled or disabled, the state of w rite protection, quad spi setting, security registe r lock status, erase/program suspend status, output drive r strength, power-up and current address mode. the write status register instruction can be used to co nfigure the device write protection features, quad spi setting, security register otp locks, hold/reset f unctions, output driver strength and power-up addre ss mode. write access to the status register is contro lled by the state of the non-volatile status regist er protect bits (srp, srl), the write enable instructi on, and during standard/dual spi operations, the /w p pin. 7.1 status registers figure 4a. status register-1 erase/write in progress (busy) C status only busy is a read only bit in the status register (s0) that is set to a 1 state when the device is execut ing a page program, quad page program, sector erase, bloc k erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further instructi ons except for the read status register and erase/progr am suspend instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when the program, erase or write status/security register instruction has comp leted, the busy bit will be cleared to a 0 state indicatin g the device is ready for further instructions. write enable latch (wel) C status only write enable latch (wel) is a read only bit in the status register (s1) that is set to 1 after executi ng a write enable instruction. the wel status bit is cleared t o 0 when the device is write disabled. a write disa ble state occurs upon power-up or after any of the foll owing instructions: write disable, page program, qu ad page program, sector erase, block erase, chip erase , write status register, erase security register an d program security register. block protect bits (bp2, bp1, bp0) C volatile/non-volatile writable the block protect bits (bp2, bp1, bp0) are non-vola tile read/write bits in the status register (s4, s3 , and s2) that provide write protection control and statu s. block protect bits can be set using the write st atus register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the facto ry default setting for the block protection bits is 0, none of the array protected.
w25q32jv - 15 - top/bottom block protect (tb) C volatile/non-volatile writable the non-volatile top/bottom bit (tb) controls if th e block protect bits (bp2, bp1, bp0) protect from t he top (tb=0) or the bottom (tb=1) of the array as shown i n the status register memory protection table. the factory default setting is tb=0. the tb bit can be set with the write status register instruction depe nding on the state of the srp, srl and wel bits. sector/block protect bit (sec) C volatile/non-volatile writable the non-volatile sector/block protect bit (sec) con trols if the block protect bits (bp2, bp1, bp0) pro tect either 4kb sectors (sec=1) or 64kb blocks (sec=0) i n the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection t able. the default setting is sec=0. complement protect (cmp) C volatile/non-volatile writable the complement protect bit (cmp) is a non-volatile read/write bit in the status register (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by s ec, tb, bp2, bp1 and bp0 will be reversed. for inst ance, when cmp=0, a top 64kb block can be protected while the rest of the array is not; when cmp=1, the top 64kb block will become unprotected while the rest o f the array become read-only. please refer to the s tatus register memory protection table for details. the d efault setting is cmp=0.
w25q32jv publication release date: november 18, 2014 - 16 - preliminary-revision a1 status register protect (srp, srl) the status register protect bits (srp) are non-vola tile read/write bits in the status register (s7). t he srp bit controls the method of write protection: softwa re protection or hardware protection. the status re gister lock bits (srl) are non-volatile/volatile read/writ e bits in the status register (s8). the srl bit con trols the method of write protection: temporary lock-down or permanently one time program. srp /wp status protection description 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction, wel=1. [factory default] 1 0 hardware protected when /wp pin is low the status register cant be written to. 1 hardware unprotected when /wp pin is high the status register can be written to after a write enable instruction, wel=1. srl status register lock description 0 non-lock status register is unlocked 1 lock-down (1) (temporary/volatile) status register is locked by standard status regist er write command and cant be written to again until t he next power-down, power-up cycle. one time program (2) (permanently/non-volatile) status register is permanently locked by special command flow * and cant be written to note: 1. when srl =1, a power-down, power-up cycle will change srl =0 state. 2. please contact winbond for details regarding th e special instruction sequence.
w25q32jv - 17 - figure 4b. status register-2 erase/program suspend status (sus) C status only the suspend status bit is a read only bit in the st atus register (s15) that is set to 1 after executin g a erase/program suspend (75h) instruction. the sus st atus bit is cleared to 0 by erase/program resume (7ah) instruction as well as a power-down, power-up cycle. security register lock bits (lb3, lb2, lb1) C volatile/non-volatile otp writable the security register lock bits (lb3, lb2, lb1) are non-volatile one time program (otp) bits in status register (s13, s12, s11) that provide the write pro tect control and status to the security registers. the default state of lb3-1 is 0, security registers are unlocked. lb3-1 can be set to 1 individually using the write status register instruction. lb3-1 are one ti me programmable (otp), once its set to 1, the corresponding 256-byte security register will becom e read-only permanently. quad enable (qe) C volatile/non-volatile writable the quad enable (qe) bit is a non-volatile read/wri te bit in the status register (s9) that allows quad spi. when the qe bit is set to a 0 state (factory defaul t for part numbers with ordering options im), the /wp pin and /hold are enabled. when the qe bit is set to a 1(factory default for quad enabled part numbers wit h ordering option iq), the quad io2 and io3 pins ar e enabled, and /wp and /hold functions are disabled . warning: if the /wp or /hold pins are tied directly to the power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1. s 15 s 14 s13 s 12 s 11 s10 s 9 s 8 sus cmp lb 3 lb 2 lb 1 (r) qe sr l s tatus register lock ( volatile / non- volatile writable ) complement protect ( volatile / non- volatile writable ) security register lock bits ( volatile / non- volatile otp writable ) reserved quad enable ( volatile / non- volatile writable ) suspend status ( status -only)
w25q32jv publication release date: november 18, 2014 - 18 - preliminary-revision a1 figure 4c. status register-3 write protect selection (wps) C volatile/non-volatile writable the wps bit is used to select which write protect s cheme should be used. when wps=0, the device will use the combination of cmp, sec, tb, bp[2:0] bits t o protect a specific area of the memory array. when wps=1, the device will utilize the individual block locks to protect any individual sector or blocks. the default value for all individual block lock bits is 1 upon device power on or after reset. output driver strength (drv1, drv0) C volatile/non-volatile writable the drv1 & drv0 bits are used to determine the outp ut driver strength for the read operations. drv1, drv0 driver strength 0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default) /hold or /reset pin function (hold/rst) C volatile/non-volatile writable the hold/rst bit is used to determine whether /hold or /reset function should be implemented on the hardware pin for 8-pin packages. when hold/rst=0 (f actory default), the pin acts as /hold; when hold/rst=1, the pin acts as /reset. however, /hold or /reset functions are only available when qe=0. if qe is set to 1, the /hold and /reset funct ions are disabled, the pin acts as a dedicated data i/o pin. reserved bits C non functional there are a few reserved status register bits that may be read out as a 0 or 1. it is recommended to ignore the values of those bits. during a write st atus register instruction, the reserved bits can b e written as 0, but there will not be any effects.
w25q32jv - 19 - status register memory protection (wps = 0, cmp = 0 ) status register (1) w25q32jv (32m-bit) memory protection (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 none none none none 0 0 0 0 1 63 3f0000h C 3fffffh 64kb upper 1/64 0 0 0 1 0 62 and 63 3e0000h C 3fffffh 128kb upper 1/32 0 0 0 1 1 60 thru 63 3c0000h C 3fffffh 256kb upper 1/16 0 0 1 0 0 56 thru 63 380000h C 3fffffh 512kb upper 1/8 0 0 1 0 1 48 thru 63 300000h C 3fffffh 1mb upper 1/4 0 0 1 1 0 32 thru 63 200000h C 3fffffh 2mb upper 1/2 0 1 0 0 1 0 000000h C 00ffffh 64kb lower 1/64 0 1 0 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/32 0 1 0 1 1 0 thru 3 000000h C 03ffffh 256kb lower 1/16 0 1 1 0 0 0 thru 7 000000h C 07ffffh 512kb lower 1/8 0 1 1 0 1 0 thru 15 000000h C 0fffffh 1mb lower 1/4 0 1 1 1 0 0 thru 31 000000h C 1fffffh 2mb lower 1/2 x x 1 1 1 0 thru 63 000000h C 3fffffh 4mb all 1 0 0 0 1 63 3ff000h C 3fffffh 4kb u - 1/1024 1 0 0 1 0 63 3fe000h C 3fffffh 8kb u - 1/512 1 0 0 1 1 63 3fc000h C 3fffffh 16kb u - 1/256 1 0 1 0 x 63 3f8000h C 3fffffh 32kb u - 1/128 1 1 0 0 1 0 000000h C 000fffh 4kb l - 1/1024 1 1 0 1 0 0 000000h C 001fffh 8kb l - 1/512 1 1 0 1 1 0 000000h C 003fffh 16kb l - 1/256 1 1 1 0 x 0 000000h C 007fffh 32kb l - 1/128 notes: 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memo ry region that contains protected data portion, thi s command will be ignored.
w25q32jv publication release date: november 18, 2014 - 20 - preliminary-revision a1 status register memory protection (wps = 0, cmp = 1 ) status register (1) w25q32jv (32m-bit) memory protection (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 0 thru 63 000000h C 3fffffh 4mb all 0 0 0 0 1 0 thru 62 000000h C 3effffh 4,032kb lower 63/64 0 0 0 1 0 0 and 61 000000h C 3dffffh 3,968kb lower 31/32 0 0 0 1 1 0 thru 59 000000h C 3bffffh 3,840kb lower 15/16 0 0 1 0 0 0 thru 55 000000h C 37ffffh 3,584kb lower 7/8 0 0 1 0 1 0 thru 47 000000h C 2fffffh 3mb lower 3/4 0 0 1 1 0 0 thru 31 000000h C 1fffffh 2mb lower 1/2 0 1 0 0 1 1 thru 63 010000h C 3fffffh 4,032kb upper 63/64 0 1 0 1 0 2 and 63 020000h C 3fffffh 3,968kb upper 31/32 0 1 0 1 1 4 thru 63 040000h C 3fffffh 3,840kb upper 15/16 0 1 1 0 0 8 thru 63 080000h C 3fffffh 3,584kb upper 7/8 0 1 1 0 1 16 thru 63 100000h C 3fffffh 3mb upper 3/4 0 1 1 1 0 32 thru 63 200000h C 3fffffh 2mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 63 000000h C 3fefffh 4,092kb l - 1023/10 24 1 0 0 1 0 0 thru 63 000000h C 3fdfffh 4,088kb l - 511/512 1 0 0 1 1 0 thru 63 000000h C 3fbfffh 4,080kb l - 255/256 1 0 1 0 x 0 thru 63 000000h C 3f7fffh 4,064kb l - 127/128 1 1 0 0 1 0 thru 63 001000h C 3fffffh 4,092kb u - 1023/10 24 1 1 0 1 0 0 thru 63 002000h C 3fffffh 4,088kb u - 511/512 1 1 0 1 1 0 thru 63 004000h C 3fffffh 4,080kb u - 255/256 1 1 1 0 x 0 thru 63 008000h C 3fffffh 4,064kb u - 127/128 notes: 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memo ry region that contains protected data portion, thi s command will be ignored .
w25q32jv - 21 - individual block memory protection (wps=1) figure 4d. individual block/sector locks notes: 1. individual block/sector protection is only valid when wps=1. 2. all individual block/sector lock bits are set to 1 by default after power up, all memory array is p rotected.
w25q32jv publication release date: november 18, 2014 - 22 - preliminary-revision a1 8. instructions the standard/dual/quad spi instruction set of the w 25q32jv consists of 48 basic instructions that are fully controlled through the spi bus (see instructi on set table1-2). instructions are initiated with t he falling edge of chip select (/cs). the first byte of data c locked into the di input provides the instruction c ode. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to s everal bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diag rams for each instruction are included in figures 5 through 57. all read instructions can be completed after an y clocked bit. however, all instructions that write , program or erase must complete on a byte boundary ( /cs driven high after a full 8-bits have been clock ed) otherwise the instruction will be ignored. this fea ture further protects the device from inadvertent w rites. additionally, while the memory is being programmed or erased, or when the status register is being wri tten, all instructions except for read status register wi ll be ignored until the program or erase cycle has completed. 8.1 device id and instruction set tables manufacturer and device identification manufacturer id (mf7 - mf0) winbond serial flash efh device id (id7 - id0) (id15 - id0) instruction abh, 90h, 92h, 94h 9fh w25q32jv 15h 4016h
w25q32jv - 23 - instruction set table 1 (standard spi instructions) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 number of clock (1-1-1) 8 8 8 8 8 8 8 write enable 06h volatile sr write enable 50h write disable 04h release power-down / id abh dummy dummy dummy (id7-id0) (2) manufacturer/device id 90h dummy dummy 00h (mf7-mf0) (id7-id0) jedec id 9fh (mf7-mf0) (id15-id8) (id7-id0) read unique id 4bh dummy dummy dummy dummy (uid63-0) read data 03h a23-a16 a15-a8 a7-a0 (d7-d0) fast read 0bh a23-a16 a15-a8 a7-a0 dummy (d7-d0) page program 02h a23-a16 a15-a8 a7-a0 d7-d0 d7-d0 (3) sector erase (4kb) 20h a23-a16 a15-a8 a7-a0 block erase (32kb) 52h a23-a16 a15-a8 a7-a0 block erase (64kb) d8h a23-a16 a15-a8 a7-a0 chip erase c7h/60h read status register-1 05h (s7-s0) (2) write status register-1 (4) 01h (s7-s0) (4) read status register-2 35h (s15-s8) (2) write status register-2 31h (s15-s8) read status register-3 15h (s23-s16) (2) write status register-3 11h (s23-s16) read sfdp register 5ah 00h 00h a7Ca0 dummy (d7-0) erase security register (5) 44h a23-a16 a15-a8 a7-a0 program security register (5) 42h a23-a16 a15-a8 a7-a0 d7-d0 d7-d0 (3) read security register (5) 48h a23-a16 a15-a8 a7-a0 dummy (d7-d0) global block lock 7eh global block unlock 98h read block lock 3dh a23-a16 a15-a8 a7-a0 (l7-l0) individual block lock 36h a23-a16 a15-a8 a7-a0 individual block unlock 39h a23-a16 a15-a8 a7-a0 erase / program suspend 75h erase / program resume 7ah power-down b9h enable reset 66h reset device 99h
w25q32jv publication release date: november 18, 2014 - 24 - preliminary-revision a1 instruction set table 2 (dual/quad spi instructions ) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 number of clock (1-1-2) 8 8 8 8 4 4 4 4 fast read dual output 3bh a23-a16 a15-a8 a7-a0 dummy dummy (d7-d0) (7) number of clock (1-2-2) 8 4 4 4 4 4 4 4 fast read dual i/o bbh a23-a16 (6) a15-a8 (6) a7-a0 (6) dummy (12) (d7-d0) (7) mftr./device id dual i/o 92h a23-a16 (6) a15-a8 (6) 00 (6) dummy (12) (mf7-mf0) (id7-id0) (7) number of clock (1-1-4) 8 8 8 8 2 2 2 2 quad input page program 32h a23-a16 a15-a8 a7-a0 (d7-d0) (9) (d7-d0) (3) fast read quad output 6bh a23-a16 a15-a8 a7-a0 dummy dummy dummy (d7-d0) (9) number of clock (1-4-4) 8 2 2 2 2 2 2 2 mftr./device id quad i/o 94h a23-a16 (8) a15-a8 (8) 00 (8) dummy (12) dummy dummy (mf7-mf0) (9) fast read quad i/o ebh a23-a16 a15-a8 a7-a0 dummy (12) dummy dummy (d7-d0) set burst with wrap 77h dummy dummy dummy w8-w0 notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ( ) indicate data output from the device on either 1, 2 or 4 io pins. 2. the status register contents and device id will repeat continuously until /cs terminates the instru ction. 3. at least one byte of data input is required for page program, quad page program and program securit y registers, up to 256 bytes of data input. if more t han 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page a nd overwrite previously sent data. 4. write status register-1 (01h) can also be used t o program status register-1&2, see section 8.2.5. 5. security register address: security register 0: a23-16 = 00h; a15- 8 = 00h; a7-0 = byte address security register 1: a23-16 = 00h; a15- 8 = 10h; a7-0 = byte address security register 2: a23-16 = 00h; a15- 8 = 20h; a7-0 = byte address security register 3: a23-16 = 00h; a15- 8 = 30h; a7-0 = byte address 6. dual spi address input format: io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 7. dual spi data output format: io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 8. quad spi address input format: set burst with wrap input format: io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 9. quad spi data input/output format: io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 10. fast read quad i/o data output format: io0 = (x, x, x, x, d4, d0, d4, d0) io1 = (x, x, x, x, d5, d1, d5, d1) io2 = (x, x, x, x, d6, d2, d6, d2) io3 = (x, x, x, x, d7, d3, d7, d3) 11. the first dummy is m7-m0 should be set to ffh
w25q32jv - 25 - 8.2 instruction descriptions write enable (06h) the write enable instruction (figure 5) sets the wr ite enable latch (wel) bit in the status register t o a 1. the wel bit must be set prior to every page program , quad page program, sector erase, block erase, chip erase, write status register and erase/program security registers instruction. the write enable instruction is entered by driving /cs low, shifting the instruction code 06h into the data input (di ) pin on the rising edge of clk, and then driving /cs high. figure 5. write enable instruction for spi mode write enable for volatile status register (50h) the non-volatile status register bits described in section 7.1 can also be written to as volatile bits . this gives more flexibility to change the system configu ration and memory protection schemes quickly withou t waiting for the typical non-volatile bit write cycl es or affecting the endurance of the status registe r non- volatile bits. to write the volatile values into th e status register bits, the write enable for volati le status register (50h) instruction must be issued prior to a write status register (01h) instruction. write en able for volatile status register instruction (figure 6) wil l not set the write enable latch (wel) bit, it is o nly valid for the write status register instruction to change the volatile status register bit values. figure 6. write enable for volatile status register instruction for spi mode /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance
w25q32jv publication release date: november 18, 2014 - 26 - preliminary-revision a1 write disable (04h) the write disable instruction (figure 7) resets the write enable latch (wel) bit in the status registe r to a 0. the write disable instruction is entered by driv ing /cs low, shifting the instruction code 04h into the d i pin and then driving /cs high. note that the wel bi t is automatically reset after power-up and upon completion of the write status register, erase/prog ram security registers, page program, quad page program, sector erase, block erase, chip erase and reset instructions. figure 7. write disable instruction for spi mod e /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance
w25q32jv - 27 - read status register-1 (05h), status register-2 (35 h) & status register-3 (15h) the read status register instructions allow the 8-b it status registers to be read. the instruction is entered by driving /cs low and shifting the instruction cod e 05h for status register-1, 35h for status reg ister-2 or 15h for status register-3 into the di pin on t he rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of cl k with most significant bit (msb) first as shown in figure 8. refer to section 7.1 for status register descrip tions. the read status register instruction may be used at any time, even while a program, erase or write sta tus register cycle is in progress. this allows the busy status bit to be checked to determine when the cyc le is complete and if the device can accept another in struction. the status register can be read continuo usly, as shown in figure 8. the instruction is completed by driving /cs high. figure 8a. read status register instruction (spi mo de) write status register-1 (01h), status register-2 (3 1h) & status register-3 (11h) the write status register instruction allows the st atus registers to be written. the writable status r egister bits include: srp, sec, tb, bp[2:0] in status regis ter-1; cmp, lb[3:1], qe, srl in status register-2; hold/rst, drv1, drv0, wps in status register-3. all other status register bit locations are read-only and will not be affected by the write status regist er instruction. lb[3:1] are non-volatile otp bits, once it is set to 1, it cannot be cleared to 0. to write non-volatile status register bits, a stand ard write enable (06h) instruction must previously have been executed for the device to accept the write st atus register instruction (status register bit wel must equal 1). once write enabled, the instruction is en tered by driving /cs low, sending the instruction c ode 01h/31h/11h, and then writing the status register data byte as illustrated in figure 9a & 9b. to write volatile status register bits, a write ena ble for volatile status register (50h) instruction must have been executed prior to the write status register in struction (status register bit wel remains 0). howe ver, srl and lb[3:1] cannot be changed from 1 to 0 b ecause of the otp protection for these bits. upon power off or the execution of a software/hardware r eset, the volatile status register bit values will be lost, and the non-volatile status register bit values wil l be restored. during non-volatile status register write operation (06h combined with 01h/31h/11h), after /cs is driv en high, the self-timed write status register cycle wi ll commence for a time duration of t w (see ac characteristics). while the write status register c ycle is in progress, the read status register instr uction may still be accessed to check the status of the bu sy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished a nd ready to accept other instructions again. after the write status register cycle has finished, the write enable latch (wel) bit in the status register will be cleared to 0.
w25q32jv publication release date: november 18, 2014 - 28 - preliminary-revision a1 during volatile status register write operation (50 h combined with 01h/31h/11h), after /cs is driven h igh, the status register bits will be refreshed to the n ew values within the time period of t shsl2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. refer to section 7.1 for status register descriptio ns. figure 9a. write status register-1/2/3 instruction (spi mode) the w25q32jv is also backward compatible to winbond s previous generations of serial flash memories, in which the status register-1&2 can be written usi ng a single write status register-1 (01h) command . to complete the write status register-1&2 instructi on, the /cs pin must be driven high after the sixte enth bit of data that is clocked in as shown in figure 9 c & 9d. if /cs is driven high after the eighth cloc k, the write status register-1 (01h) instruction will only progr am the status register-1, the status register-2 wil l not be affected (previous generations will clear cmp an d qe bits). figure 9c. write status register-1/2 instruction (s pi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb *
w25q32jv - 29 - read data (03h) the read data instruction allows one or more data b ytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h follo wed by a 24-bit address (a23-a0) into the di pin. the code a nd address bits are latched on the rising edge of t he clk pin. after the address is received, the data by te of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automat ically incremented to the next higher address after each b yte of data is shifted out allowing for a continuou s stream of data. this means that the entire memory c an be accessed with a single instruction as long as the clock continues. the instruction is completed by dr iving /cs high. the read data instruction sequence is shown in figu re 14. if a read data instruction is issued while a n erase, program or write cycle is in process (busy=1 ) the instruction is ignored and will not have any effects on the current cycle. the read data instruc tion allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). the read data (03h) instruction is only supported i n standard spi mode. figure 14. read data instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
w25q32jv publication release date: november 18, 2014 - 30 - preliminary-revision a1 fast read (0bh) the fast read instruction is similar to the read da ta instruction except that it can operate at the hi ghest possible frequency of f r (see ac electrical characteristics). this is accom plished by adding eight dummy clocks after the 24-bit address as shown in figure 16. the dummy clocks allow the devices internal cir cuits additional time for setting up the initial address. during the dummy clocks the data value on the do p in is a dont care. figure 16a. fast read instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
w25q32jv - 31 - fast read dual output (3bh) the fast read dual output (3bh) instruction is simi lar to the standard fast read (0bh) instruction exc ept that data is output on two pins; io 0 and io 1 . this allows data to be transferred at twice the r ate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code from flash to ram upon power-up or for applications that cache co de-segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accom plished by adding eight dummy clocks after the 24-bit address as shown in figure 18. the dummy clocks allow the device's internal ci rcuits additional time for setting up the initial address. the input data during the dummy clocks is dont c are. however, the io 0 pin should be high-impedance prior to the falling edge of the first data out clock. figure 18. fast read dual output instruction (spi m ode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
w25q32jv publication release date: november 18, 2014 - 32 - preliminary-revision a1 fast read quad output (6bh) the fast read quad output (6bh) instruction is simi lar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . the quad enable (qe) bit in status register- 2 must be set to 1 before the device will accept th e fast read quad output instruction. the fast read quad output instruction allows data to be transferr ed at four times the rate of standard spi devices. the fast read quad output instruction can operate a t the highest possible frequency of f r (see ac electrical characteristics). this is accomplished b y adding eight dummy clocks after the 24-bit addr ess as shown in figure 20. the dummy clocks allow the d evice's internal circuits additional time for setti ng up the initial address. the input data during the dumm y clocks is dont care. however, the io pins shou ld be high-impedance prior to the falling edge of the fir st data out clock. figure 20. fast read quad output instruction (spi m ode only) /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
w25q32jv - 33 - fast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23-0) two bits per clock. this r educed instruction overhead may allow for code exec ution (xip) directly from the dual spi in some applicatio ns. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further redu ce instruction overhead through setting the contin uous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 22a. the upper nibble of the (m7-4) controls the length of the next fast rea d dual i/o instruction through the inclusion or exc lusion of the first byte instruction code. the lower nibbl e bits of the (m3-0) are dont care (x). however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5-4 = (1,0), th en the next fast read dual i/o instruction (after / cs is raised and then lowered) does not require the bbh i nstruction code, as shown in figure 22b. this reduc es the instruction sequence by eight clocks and allows the read address to be immediately entered after / cs is asserted low. if the continuous read mode bits m5-4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal ope ration. it is recommended to input ffffh on io0 for the nex t instruction (16 clocks), to ensure m4 = 1 and ret urn the device to normal operation. figure 22a. fast read dual i/o instruction (initial instruction or previous m5-4 1 10, spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
w25q32jv publication release date: november 18, 2014 - 34 - preliminary-revision a1 figure 22b. fast read dual i/o instruction (previou s instruction set m5-4 = 10, spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 * = msb *
w25q32jv - 35 - fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy clocks are required in spi mode prior to the data output. the quad i/o dramatically reduces instruction overh ead allowing faster random access for code execution (x ip) directly from the quad spi. the quad enable bit (qe) of status register-2 must be set to enable the fast read quad i/o instruction. fast read quad i/o with continuous read mode the fast read quad i/o instruction can further redu ce instruction overhead through setting the contin uous read mode bits (m7-0) after the input address bits (a23-0), as shown in figure 24a. the upper nibble of the (m7-4) controls the length of the next fast rea d quad i/o instruction through the inclusion or exc lusion of the first byte instruction code. the lower nibbl e bits of the (m3-0) are dont care (x). however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5-4 = (1,0), th en the next fast read quad i/o instruction (after / cs is raised and then lowered) does not require the eb h instruction code, as shown in figure 24b. this re duces the instruction sequence by eight clocks and allows the read address to be immediately entered after / cs is asserted low. if the continuous read mode bits m5-4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal ope ration. it is recommended to input ffh on io0 for the next instruction (8 clocks), to ensure m4 = 1 and return the device to normal operation. figure 24a. fast read quad i/o instruction (initial instruction or previous m5-4 1 10, spi mode) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
w25q32jv publication release date: november 18, 2014 - 36 - preliminary-revision a1 figure 24b. fast read quad i/o instruction (previou s instruction set m5-4 = 10, spi mode) fast read quad i/o with 8/16/32/64-byte wrap aroun d in standard spi mode the fast read quad i/o instruction can also be used to access a specific portion within a page by issu ing a set burst with wrap (77h) command prior to ebh. the set burst with wrap (77h) command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byt e page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications tha t use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/ 16/32/64-byte) of data without issuing multiple rea d commands. the set burst with wrap instruction allows three wrap bits, w6-4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6-5 a re used to specify the length of the wrap around se ction within a page. refer to section 8.2.37 for detail d escriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 dummy dummy
w25q32jv - 37 - set burst with wrap (77h) in standard spi mode, the set burst with wrap (77h) instruction is used in conjunction with fast read quad i/o instruction to access a fixed length of 8 /16/32/64-byte section within a 256-byte page. cert ain applications can benefit from this feature and impr ove the overall system code execution performance. similar to a quad i/o instruction, the set burst wi th wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h follow ed by 24 dummy bits and 8 wrap bits, w7-0. the instruction sequence is shown in figure 28. wrap bi t w7 and the lower nibble w3-0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8-byte no n/a 0 1 yes 16-byte no n/a 1 0 yes 32-byte no n/a 1 1 yes 64-byte no n/a once w6-4 is set by a set burst with wrap instructi on, all the following fast read quad i/o instruct ion will use the w6-4 setting to access the 8/16/32/64- byte section within any page. to exit the wrap aro und function and return to normal read operation, anoth er set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on o r after a software/hardware reset is 1. figure 28. set burst with wrap instruction (spi mod e only) wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
w25q32jv publication release date: november 18, 2014 - 38 - preliminary-revision a1 page program (02h) the page program instruction allows from one byte t o 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write e nable instruction must be executed before the devic e will accept the page program instruction (status re gister bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h fo llowed by a 24-bit address (a23-a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the i nstruction while data is being sent to the device. the page program instruction sequence is shown in figure 29. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceeds the remaini ng page length, the addressing will wrap to the beginn ing of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks cannot exceed the remaining p age length. if more than 256 bytes are sent to the devi ce the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs p in must be driven high after the eighth bit of the last byte has been latched. if this is not done the page prog ram instruction will not be executed. after /cs is driven high, the self-timed page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is i n progress, the read status register instruction ma y still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished an d the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status register is c leared to 0. the page program instruction will not be exec uted if the addressed page is protected by the bloc k protect (cmp, sec, tb, bp2, bp1, and bp0) bits or t he individual block/sector locks. figure 29a. page program instruction (spi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q32jv - 39 - quad input page program (32h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applications th at have slow clock speeds <5mhz. systems with faster clock speed will not realize much benefit fo r the quad page program instruction since the inher ent page program time is much greater than the time it take to clock-in the data. to use quad page program the quad enable (qe) bit i n status register-2 must be set to 1. a write enabl e instruction must be executed before the device will accept the quad page program instruction (status register-1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 32h followed by a 24-bit address (a23-a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instructio n while data is being sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 30. figure 30. quad input page program instruction (spi mode only) /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
w25q32jv publication release date: november 18, 2014 - 40 - preliminary-revision a1 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be execut ed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code 20h followed a 24-bit sector address (a23-a0). the sector erase instruction sequence is shown in figure 31a & 31b. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the sector erase instruction will not be executed. afte r /cs is driven high, the self-timed sector erase i nstruction will commence for a time duration of t se (see ac characteristics). while the sector erase c ycle is in progress, the read status register instruction may still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the sector erase cy cle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the writ e enable latch (wel) bit in the status register is cleared t o 0. the sector erase instruction will not be execu ted if the addressed page is protected by the block protec t (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 31a. sector erase instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32jv - 41 - 32kb block erase (52h) the block erase instruction sets all memory within a specified block (32k-bytes) to the erased state o f all 1s (ffh). a write enable instruction must be execut ed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code 52h followed a 24-bit block address (a23-a0). the block erase inst ruction sequence is shown in figure 32a & 32b. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase ins truction will commence for a time duration of t be 1 (see ac characteristics). while the block erase c ycle is in progress, the read status register instruction may still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the block erase cyc le and becomes a 0 when the cycle is finished and t he device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared t o 0. the block erase instruction will not be execut ed if the addressed page is protected by the block protec t (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 32a. 32kb block erase instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32jv publication release date: november 18, 2014 - 42 - preliminary-revision a1 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k-bytes) to the erased state o f all 1s (ffh). a write enable instruction must be execut ed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code d8h followed a 24-bit block address (a23-a0). the block erase instruction sequence is shown in figure 33a & 33b. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase ins truction will commence for a time duration of t be (see ac characteristics). while the block erase cy cle is in progress, the read status register instruction may still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the block erase cyc le and becomes a 0 when the cycle is finished and t he device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared t o 0. the block erase instruction will not be execut ed if the addressed page is protected by the block protec t (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 33a. 64kb block erase instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32jv - 43 - chip erase (c7h / 60h) the chip erase instruction sets all memory within t he device to the erased state of all 1s (ffh). a wr ite enable instruction must be executed before the devi ce will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting t he instruction code c7h or 60h. the chip erase ins truction sequence is shown in figure 34. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the chip er ase instruction will not be executed. after /cs is driv en high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cyc le is in progress, the read status register instruction may still be accessed t o check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when fi nished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the st atus register is cleared to 0. the chip erase instructio n will not be executed if any memory region is prot ected by the block protect (cmp, sec, tb, bp2, bp1, and b p0) bits or the individual block/sector locks. figure 24. chip erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3
w25q32jv publication release date: november 18, 2014 - 44 - preliminary-revision a1 erase / program suspend (75h) the erase/program suspend instruction 75h, allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program/erase data to, any other sectors o r blocks. the erase/program suspend instruction seque nce is shown in figure 35a & 35b. the write status register instruction (01h) and era se instructions (20h, 52h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is vali d only during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write status register instruction (01h) and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the p age program or quad page program operation. the erase/program suspend instruction 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page progr am operation is on-going. if the sus bit equals to 1 o r the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximum of time of t sus (see ac characteristics) is required to suspend t he erase or program operation. the busy bit in the sta tus register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase/program suspend . for a previously resumed erase/program operation, i t is also required that the suspend instruction 75 h is not issued earlier than a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off during the erase/program suspe nd state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector o r block that was being suspended may become corrupted. it i s recommended for the user to implement system design techniques against the accidental power inte rruption and preserve data integrity during erase/program suspend state. figure 35a. erase/program suspend instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
w25q32jv - 45 - erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an er ase/program suspend. the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. after issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or th e busy bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program resume instruction sequence is shown in figure 36a & 36b. resume instruction is ignored if the previous erase /program suspend operation was interrupted by unexpected power off. it is also required that a su bsequent erase/program suspend instruction not to b e issued within a minimum of time of t sus following a previous resume instruction. figure 36a. erase/program resume instruction (spi m ode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase
w25q32jv publication release date: november 18, 2014 - 46 - preliminary-revision a1 power-down (b9h) although the standby current during normal operatio n is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as shown i n figure 37a & 37b. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the power-d own instruction will not be executed. after /cs is driv en high, the power-down state will entered within t he time duration of t dp (see ac characteristics). while in the power-down state only the release power-down / device id (abh) instruction, which restores the dev ice to normal operation, will be recognized. all ot her instructions are ignored. this includes the read st atus register instruction, which is always availabl e during normal operation. ignoring all but one instr uction makes the power down state a useful conditio n for securing maximum write protection. the device alway s powers-up in the normal operation with the standb y current of icc1. figure 37a. deep power-down instruction (spi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current
w25q32jv - 47 - release power-down / device id (abh) the release from power-down / device id instruction is a multi-purpose instruction. it can be used to release the device from the power-down state, or ob tain the devices electronic identification (id) num ber. to release the device from the power-down state, th e instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in figure 38a & 38b. release from power-down will take the time duration of t res1 (see ac characteristics) before the device will re sume normal operation and other instructions are accepted. the /cs pin mu st remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the /cs pin low and shifting the instructio n code abh followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of cl k with most significant bit (msb) first. the device id value for the w25q32jv is listed in manufacturer and devi ce identification table. the device id can be read continuously. the instruction is completed by drivi ng /cs high. when used to release the device from the power-down state and obtain the device id, the instruction is the same as previously described, and shown in figure 3 8c & 38d, except that after /cs is driven high it m ust remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power-down / devi ce id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effect s on the current cycle. figure 38a. release power-down instruction (spi mod e) figure 38c. release power-down / device id instruct ion (spi mode) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb *
w25q32jv publication release date: november 18, 2014 - 48 - preliminary-revision a1 read manufacturer / device id (90h) the read manufacturer/device id instruction is an a lternative to the release from power-down / device id instruction that provides both the jedec assigne d manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by drivin g the /cs pin low and shifting the instruction code 90h followed by a 24-bit address (a23-a0) of 000000h. a fter which, the manufacturer id for winbond (efh) a nd the device id are shifted out on the falling edge o f clk with most significant bit (msb) first as show n in figure 39. the device id values for the w25q32jv ar e listed in manufacturer and device identification table. the instruction is completed by driving /cs high. figure 39. read manufacturer / device id instructio n (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
w25q32jv - 49 - read manufacturer / device id dual i/o (92h) the read manufacturer / device id dual i/o instruct ion is an alternative to the read manufacturer / de vice id instruction that provides both the jedec assigne d manufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruct ion is similar to the fast read dual i/o instructio n. the instruction is initiated by driving the /cs pin low and shifting the instruction code 92h followed b y a 24-bit address (a23-a0) of 000000h, but with the capabilit y to input the address bits two bits per clock. aft er which, the manufacturer id for winbond (efh) and th e device id are shifted out 2 bits per clock on the falling edge of clk with most significant bits (msb ) first as shown in figure 40. the device id values for the w25q32jv are listed in manufacturer and device identification table. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by drivi ng /cs high. figure 40. read manufacturer / device id dual i/o i nstruction (spi mode only) note: the continuous read mode bits m(7-0) must be set to fxh to be compatible with fast read dual i/o ins truction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
w25q32jv publication release date: november 18, 2014 - 50 - preliminary-revision a1 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruct ion is an alternative to the read manufacturer / de vice id instruction that provides both the jedec assigne d manufacturer id and the specific device id at 4x speed. the read manufacturer / device id quad i/o instruct ion is similar to the fast read quad i/o instructio n. the instruction is initiated by driving the /cs pin low and shifting the instruction code 94h follow ed by a four clock dummy cycles and then a 24-bit address ( a23-a0) of 000000h, but with the capability to inpu t the address bits four bits per clock. after which, the manufacturer id for winbond (efh) and the devic e id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first a s shown in figure 41. the device id values for the w25q32jv are listed in manufacturer and device identificati on table. the manufacturer and device ids can be read continuously, alternating from one to the other. th e instruction is completed by driving /cs high. figure 41. read manufacturer / device id quad i/o i nstruction (spi mode only) note: the continuous read mode bits m(7-0) must be set to fxh to be compatible with fast read quad i/o ins truction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
w25q32jv - 51 - read unique id number (4bh) the read unique id number instruction accesses a fa ctory-set read-only 64-bit number that is unique to each w25q32jv device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read un ique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followe d by a four bytes of dummy clocks. after which, the 64- bit id is shifted out on the falling edge of clk as shown in figure 42. figure 42. read unique id number instruction (spi m ode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
w25q32jv publication release date: november 18, 2014 - 52 - preliminary-revision a1 read jedec id (9fh) for compatibility reasons, the w25q32jv provides se veral instructions to electronically determine the identity of the device. the read jedec id instructi on is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003 . the instruction is initiated by driving the /cs p in low and shifting the instruction code 9fh. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15-id8) and cap acity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first a s shown in figure 43a & 43b. for memory type and capacity values refer to manufacturer and device id entification table. figure 43a. read jedec id instruction (spi mode) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb *
w25q32jv - 53 - read sfdp register (5ah) the w25q32jv features a 256-byte serial flash disco verable parameter (sfdp) register that contains information about device configurations, available instructions and other features. the sfdp parameter s are stored in one or more parameter identification (pid) tables. currently only one pid table is speci fied, but more may be added in the future. the read sfdp register instruction is compatible with the sfdp standard initially established in 2010 for pc and o ther applications, as well as the jedec standard jesd216 that is published in 2011. most winbond spi flash memories shipped after june 2011 (date code 1124 and beyond) support the sfdp feature as specif ied in the applicable datasheet. the read sfdp instruction is initiated by driving t he /cs pin low and shifting the instruction code 5 ah followed by a 24-bit address (a23-a0) (1) into the di pin. eight dummy clocks are also req uired before the sfdp register contents are shifted out on the falli ng edge of the 40 th clk with most significant bit (msb) first as shown in figure 34. for sfdp register valu es and descriptions, please refer to the winbond application note for sfdp definition table. note 1: a23-a8 = 0; a7-a0 are used to define the st arting byte address for the 256-byte sfdp register. figure 34. read sfdp register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (5ah) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q32jv publication release date: november 18, 2014 - 54 - preliminary-revision a1 erase security registers (44h) the w25q32jv offers three 256-byte security registe rs which can be erased and programmed individually. these registers may be used by the sy stem manufacturers to store security and other impo rtant information separately from the main memory array. the erase security register instruction is similar to the sector erase instruction. a write enable ins truction must be executed before the device will accept the erase security register instruction (status registe r bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instructio n code 44h followed by a 24-bit address (a23-a0) to eras e one of the three security registers. address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security register #3 00h 0 0 1 1 0 0 0 0 dont care the erase security register instruction sequence is shown in figure 45. the /cs pin must be driven hig h after the eighth bit of the last byte has been latc hed. if this is not done the instruction will not b e executed. after /cs is driven high, the self-timed erase secu rity register operation will commence for a time du ration of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed for chec king the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when the cyc le is finished and the device is ready to accept ot her instructions again. after the erase security regist er cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the security r egister lock bits (lb3-1) in the status register-2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security re gister will be permanently locked, erase security register instruction to that register will be ignored (refe r to section 7.1.9 for detail descriptions). figure 45. erase security registers instruction (sp i mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32jv - 55 - program security registers (42h) the program security register instruction is simila r to the page program instruction. it allows from o ne byte to 256 bytes of security register data to be p rogrammed at previously erased (ffh) memory locatio ns. a write enable instruction must be executed before the device will accept the program security registe r instruction (status register bit wel= 1). the instr uction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24-bit add ress (a23-a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the i nstruction while data is being sent to the device. address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 0 0 0 0 byte addre ss security register #2 00h 0 0 1 0 0 0 0 0 byte addre ss security register #3 00h 0 0 1 1 0 0 0 0 byte addre ss the program security register instruction sequence is shown in figure 46. the security register lock b its (lb3-1) in the status register-2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be perm anently locked, program security register instructi on to that register will be ignored (see 7.1.9 for detail descriptions). figure 46. program security registers instruction ( spi mode only) /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q32jv publication release date: november 18, 2014 - 56 - preliminary-revision a1 read security registers (48h) the read security register instruction is similar t o the fast read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction c ode 48h followed by a 24-bit address (a23-a0) and eight dummy clocks into the di pin. the code and addres s bits are latched on the rising edge of the clk pi n. after the address is received, the data byte of the addressed memory location will be shifted out on t he do pin at the falling edge of clk with most significan t bit (msb) first. the byte address is automaticall y incremented to the next byte address after each byt e of data is shifted out. once the byte address rea ches the last byte of the register (byte address ffh), i t will reset to address 00h, the first byte of the register, and continue to increment. the instruction is completed by driving /cs high. the read security register instruction sequence is shown in figure 47. if a re ad security register instruction is issued while an erase, program or write cycle is in process (busy=1) the i nstruction is ignored and will not have any effects on the current cycle. the read security register instr uction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 0 0 0 0 byte addre ss security register #2 00h 0 0 1 0 0 0 0 0 byte addre ss security register #3 00h 0 0 1 1 0 0 0 0 byte addre ss figure 47. read security registers instruction (spi mode only) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q32jv - 57 - individual block/sector lock (36h) the individual block/sector lock provides an altern ative way to protect the memory array from adverse erase/program. in order to use the individual block /sector locks, the wps bit in status register-3 mus t be set to 1. if wps=0, the write protection will be determined by the combination of cmp, sec, tb, bp[ 2:0] bits in the status registers. the individual block/ sector lock bits are volatile bits. the default val ues after device power up or after a reset are 1, so the enti re memory array is being protected. to lock a specific block or sector as illustrated i n figure 4d, an individual block/sector lock comman d must be issued by driving /cs low, shifting the instruct ion code 36h into the data input (di) pin on the rising edge of clk, followed by a 24-bit address and then driving /cs high. a write enable instruction must b e executed before the device will accept the individu al block/sector lock instruction (status register b it wel= 1). figure 53a. individual block/sector lock instructio n (spi mode)
w25q32jv publication release date: november 18, 2014 - 58 - preliminary-revision a1 individual block/sector unlock (39h) the individual block/sector lock provides an altern ative way to protect the memory array from adverse erase/program. in order to use the individual block /sector locks, the wps bit in status register-3 mus t be set to 1. if wps=0, the write protection will be determined by the combination of cmp, sec, tb, bp[ 2:0] bits in the status registers. the individual block/ sector lock bits are volatile bits. the default val ues after device power up or after a reset are 1, so the enti re memory array is being protected. to unlock a specific block or sector as illustrated in figure 4d, an individual block/sector unlock co mmand must be issued by driving /cs low, shifting the ins truction code 39h into the data input (di) pin on the rising edge of clk, followed by a 24-bit address an d then driving /cs high. a write enable instruction must be executed before the device will accept the indiv idual block/sector unlock instruction (status regis ter bit wel= 1). figure 54a. individual block unlock instruction (sp i mode)
w25q32jv - 59 - read block/sector lock (3dh) the individual block/sector lock provides an altern ative way to protect the memory array from adverse erase/program. in order to use the individual block /sector locks, the wps bit in status register-3 mus t be set to 1. if wps=0, the write protection will be determined by the combination of cmp, sec, tb, bp[ 2:0] bits in the status registers. the individual block/ sector lock bits are volatile bits. the default val ues after device power up or after a reset are 1, so the enti re memory array is being protected. to read out the lock bit value of a specific block or sector as illustrated in figure 4d, a read block /sector lock command must be issued by driving /cs low, shi fting the instruction code 3dh into the data inpu t (di) pin on the rising edge of clk, followed by a 2 4-bit address. the block/sector lock bit value will be shifted out on the do pin at the falling edge of cl k with most significant bit (msb) first as shown in figure 55. if the least significant bit (lsb) is 1, the co rresponding block/sector is locked; if lsb=0, the corresponding block/sector is unlocked, erase/progr am operation can be performed. figure 55a. read block lock instruction (spi mode)
w25q32jv publication release date: november 18, 2014 - 60 - preliminary-revision a1 global block/sector lock (7eh) all block/sector lock bits can be set to 1 by the g lobal block/sector lock instruction. the command mu st be issued by driving /cs low, shifting the instruct ion code 7eh into the data input (di) pin on the rising edge of clk, and then driving /cs high. a write ena ble instruction must be executed before the device will accept the global block/sector lock instruction (st atus register bit wel= 1). figure 56. global block lock instruction for spi mo de (left) global block/sector unlock (98h) all block/sector lock bits can be set to 0 by the g lobal block/sector unlock instruction. the command must be issued by driving /cs low, shifting the ins truction code 98h into the data input (di) pin on the rising edge of clk, and then driving /cs high. a wr ite enable instruction must be executed before the device will accept the global block/sector unlock i nstruction (status register bit wel= 1). figure 57. global block unlock instruction for spi mode
w25q32jv - 61 - enable reset (66h) and reset device (99h) because of the small package and the limitation on the number of pins, the w25q32jv provide a software reset instruction instead of a dedicated reset pin. once the reset instruction is accepted, any on-goi ng internal operations will be terminated and the devi ce will return to its default power-on state and lo se all the current volatile settings, such as volatile status register bits, write enable latch (wel) status, program/erase suspend status, read parameter settin g (p7-p0), continuous read mode bit setting (m7- m0) and wrap bit setting (w6-w4). enable reset (66h) and reset (99h) instructions can be issued in spi. to avoid accidental reset, b oth instructions must be issued in sequence. any other commands other than reset (99h) after the enable reset (66h) command will disable the reset enable state. a new sequence of enable reset (66h) and reset (99h) is needed to reset the device. once t he reset command is accepted by the device, the dev ice will take approximately trst=30us to reset. during this period, no command will be accepted. data corruption may happen if there is an on-going or suspended internal erase or program operation wh en reset command sequence is accepted by the device. i t is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 58a. enable reset and reset instruction sequ ence (spi mode) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (99h) mode 0 mode 3 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (66h) high impedance
w25q32jv publication release date: november 18, 2014 - 62 - preliminary-revision a1 9. electrical characteristics 9.1 absolute maximum ratings (1) parameters symbol conditions range unit supply voltage vcc C0.6 to 4.6 v voltage applied to any pin v io relative to ground C0.6 to vcc+0.4 v transient voltage on any pin v iot <20ns transient relative to ground C2.0v to vcc+2.0v v storage temperature t stg C65 to +150 c lead temperature t lead see note (2) c electrostatic discharge voltage v esd human body model (3) C2000 to +2000 v notes: 1. this device has been designed and tested for the specified operation ranges. proper operation outsi de of these levels is not guaranteed. exposure to abso lute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 2. compliant with jedec standard j-std-20c for smal l body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous sub stances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1=100pf, r1=1500 ohms, r2=500 ohms). 9.2 operating ranges parameter symbol conditions spec unit min max supply voltage (1) vcc f r = 133mhz, f r = 50mhz 3.0 3.6 v f r = 104mhz, f r = 50mhz 2.7 3.0 v ambient temperature, operating t a industrial C40 +85 c note: 1. vcc voltage during read can operate across the m in and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q32jv - 63 - 9.3 power-up power-down timing and requirements parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 20 s time delay before write instruction t puw (1) 5 ms write inhibit threshold voltage v wi (1) 1.0 2.0 v note: 1. these parameters are characterized only. figure 58a. power-up timing and voltage levels figure 58b. power-up, power-down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time vcc time /cs must track vcc during vcc ramp up/down /cs
w25q32jv publication release date: november 18, 2014 - 64 - preliminary-revision a1 9.4 dc electrical characteristics- parameter symbol conditions spec unit min typ max input capacitance c in (1) v in = 0v (1) 6 pf output capacitance cout (1) v out = 0v (1) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 10 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc 1 15 a current read data / dual /quad 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 15 ma current read data / dual /quad 80mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 18 ma current read data / dual output read/quad output read 104mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 20 ma current write status register i cc 4 /cs = vcc 20 25 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il C0.5 vcc x 0.3 v input high voltage v ih vcc x 0.7 vcc + 0.4 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = C100 a vcc C 0.2 v notes: 1. tested on sample basis and specified through des ign and characterization data. ta = 25 c, vcc = 3. 0v. 2. checker board pattern.
w25q32jv - 65 - 9.5 ac measurement conditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.1 vcc to 0.9 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hi-z is defined as the point where data o ut is no longer driven. figure 59. ac measurement i/o waveform input and output timing reference levels input levels 0.9 vcc 0.1 vcc 0.5 vcc
w25q32jv publication release date: november 18, 2014 - 66 - preliminary-revision a1 9.6 ac electrical characteristics (6) description symbol alt spec unit min typ max clock frequency except for read data (03h) instructions (3.0v-3.6v) f r f c1 d.c. 133 mhz clock frequency except for read data (03h) instructions( 2.7v - 3.0v) f r f c2 d.c. 104 mhz clock frequency for read data instruction (03h) f r d.c. 50 mhz clock high, low time for all instructions except for read data (03h) t clh , t cll (1) 45% pc ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 45% pc ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 3 ns /cs active hold time relative to clk t chsh 3 ns /cs not active setup time relative to clk t shch 3 ns /cs deselect time (for read) t shsl 1 t csh 10 ns /cs deselect time (for erase or program or write) t shsl 2 t csh 50 ns output disable time t shqz (2) t dis 7 ns clock low to output valid 2.7v-3.6v t clqv t v 6 ns output hold time t clqx t ho 1.5 ns /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns continued C next page ac electrical characteristics ( contd)
w25q32jv - 67 - description symbol alt spec unit min typ max /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without id read t res 1 (2) 3 s /cs high to standby mode with id read t res 2 (2) 1.8 s /cs high to next instruction after suspend t sus (2) 20 s /cs high to next instruction after reset t rst (2) 30 s /reset pin low period to reset the device t reset (2) 1 (5) s write status register time t w 10 15 ms page program time t pp 0.7 3 ms sector erase time (4kb) t se 45 400 ms block erase time (32kb) t be 1 120 1,600 ms block erase time (64kb) t be 2 150 2,000 ms chip erase time t ce 10 50 s notes: 1. clock high + clock low must be less than or equa l to 1/f c . 2. value guaranteed by design and/or characterizati on, not 100% tested in production. 3. only applicable as a constraint for a write stat us register instruction when srp[1:0]=(0,1). 4. its possible to reset the device with shorter t reset (as short as a few hundred ns), a 1us minimum is r ecommended to ensure reliable operation. 5. tested on sample basis and specified through des ign and characterization data. t a = 25 c, vcc = 3.0v, 25% driver strength. 6. 4-bytes address alignment for quad read, start a ddress from [a1,a0]=(0,0).
w25q32jv publication release date: november 18, 2014 - 68 - preliminary-revision a1 9.7 serial output timing 9.8 serial input timing 9.9 /hold timing 9.10 wp timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
w25q32jv - 69 - 10. package specifications 10.1 8-pin soic 208-mil (package code ss) symbol millimeters inches min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8
w25q32jv publication release date: november 18, 2014 - 70 - preliminary-revision a1 10.2 8-pin vsop 208-mil (package code st) symbol millimeters inches min nom max min nom max a 1.00 0.039 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.75 0.80 0.85 0.030 0.031 0.033 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.127 ref 0.005 ref d 5.18 5.28 5.38 0.204 0.208 0.212 e 7.70 7.90 8.10 0.303 0.311 0.319 e1 5.18 5.28 5.38 0.204 0.208 0.212 e 1.27 0.050 l 0.50 0.65 0.80 0.020 0.026 0.031 y 0.10 0.004 0 8 0 8
w25q32jv - 71 - 10.3 8-pad wson 6x5-mm (package code zp) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.008 ref --- d 5.90 6.00 6.10 0.232 0.236 0.240 d2 3.35 3.40 3.45 0.132 0.134 0.136 e 4.90 5.00 5.10 0.193 0.197 0.201 e2 4.25 4.30 4.35 0.167 0.169 0.171 e 1.27 bsc 0.050 bsc l 0.55 0.60 0.65 0.022 0.024 0.026 y 0.00 --- 0.075 0.000 --- 0.003 note: the metal pad area on the bottom center of the pack age is not connected to any internal electrical sig nals. it can be left floating or connected to the device ground (gn d pin). avoid placement of exposed pcb vias under t he pad.
w25q32jv publication release date: november 18, 2014 - 72 - preliminary-revision a1 10.5 16-pin soic 300-mil (package code sf) symbol millimeters inches min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 --- 0.30 0.004 --- 0.012 a2 --- 2.31 --- --- 0.091 --- b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e1 7.39 7.49 7.59 0.291 0.295 0.299 e 1.27 bsc 0.050 bsc l 0.38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- --- 0.003 0 --- 8 0 --- 8
w25q32jv - 73 - 10.6 8-pin pdip 300-mil (package code da) symbol millimeters inches min nom max min nom max a --- --- 5.33 --- --- 0.210 a1 0.38 --- --- 0.015 --- --- a2 3.18 3.30 3.43 0.125 0.130 0.135 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.62 bsc 0.300 bsc e1 6.22 6.35 6.48 0.245 0.250 0.255 l 2.92 3.30 3.81 0.115 0.130 0.150 e b 8.51 9.02 9.53 0.335 0.355 0.375 0 7 15 0 7 15 d --- 2.54 --- --- 0.100 --- w --- 1.52 --- --- 0.060 --- p --- 0.46 --- --- 0.018 --- d w p
w25q32jv publication release date: november 18, 2014 - 74 - preliminary-revision a1 10.8 24-ball tfbga 8x6-mm (package code tc, 6x4 bal l array) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.010 0.012 0.014 b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.95 8.00 8.05 0.313 0.315 0.317 d1 5.00 bsc 0.197 bsc e 5.95 6.00 6.05 0.234 0.236 0.238 e1 3.00 bsc 0.118 bsc e 1.00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q32jv - 75 - 11. ordering information notes: 1. the w prefix is not included on the part marki ng. 2. only the 2 nd letter is used for the part marking; wson package type zp is not used for the part marking. 3. standard bulk shipments are in tube (shape e). p lease specify alternate packing method, such as tap e and reel (shape t) or tray (shape s), when placing orde rs. 4. for shipments with otp feature enabled, please s pecify when placing orders. w (1) 25q 32 j v xx (2) i w = winbond 25q = spiflash serial flash memory with 4kb secto rs, dual/quad i/o 32j = 32m-bit v = 2.7v to 3.6v ss = 8-pin soic 208-mil st = 8-pin vsop 208-mil sf = 16-pin soic 300-mil da = 8-pin pdip 300-mil zp = wson8 6x5-mm tc = tfbga 8x6-mm (6x4 ball array) i = industrial (-40c to +85c) (3,4) q = green package (lead-free, rohs compliant, halogen-f ree (tbba), antimony-oxide-free sb 2 o 3 ) with qe = 1 in status register-2
w25q32jv publication release date: november 18, 2014 - 76 - preliminary-revision a1 11.1 valid part numbers and top side marking the following table provides the valid part numbers for the w25q32jv spiflash memory. please contact winbond for specific availability by density and pa ckage type. winbond spiflash memories use a 12-digi t product number for ordering. however, due to limite d space, the top side marking on all packages uses an abbreviated 10-digit number. package type density product number top side markin g ss soic-8 208-mil 32m-bit w25q32jvssiq 25q32jvsiq st (1) vsop - 8 208 - mil 32m-bit w25q32jvstiq 25q32jvtiq sf soic-16 300-mil 32m-bit w25q32jvsfiq 25q32jvfiq da pdip-8 300-mil 32m-bit w25q32jvdaiq 25q32jvaiq zp wson-8 6x5-mm 32m-bit w25q32jvzpiq 25q32jviq tc (1) tfbga-24 8x6-mm (6x4 ball array) 32m-bit W25Q32JVTCIQ 25q32jvciq note: 1. these package types are special order, please co ntact winbond for more information.
w25q32jv - 77 - 12. revision history version date page description a 2014/06/30 new create datasheet a1 2014/11/18 7 18 64-66 updated tfbga ball assignment updated sr3 information updated ac electrical characteristics trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respectiv e owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, at omic energy control instruments, airplane or spaces hip instruments, transportation instruments, traffic si gnal instruments, combustion control instruments, o r for other applications intended to support or sustain l ife. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation where in personal injury, death or severe property or environmental damage co uld occur. winbond customers using or selling these products for use in such applications do so at thei r own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, mo difications or improvements to this document and the products and services described herein at a ny time, without notice.

▲Up To Search▲

Price & Availability of W25Q32JVTCIQ

	To Download W25Q32JVTCIQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .